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1 Ergebnisse
1
Time-Division Multiplexing Based System-Level FPGA Routing ..:
, In:
2020 57th ACM/IEEE Design Automation Conference (DAC)
,
Zou, Peng
;
Lin, Zhifeng
;
Shi, Xiao
... - p. 1-6 , 2020
Link:
https://doi.org/10.1109/DAC18072.2020.9218569
RT T1 <cTitle>2020 57th ACM/IEEE Design Automation Conference (DAC)</cTitle>: T1 <Title>Time-Division Multiplexing Based System-Level FPGA Routing for Logic Verification*</Title> UL https://suche.suub.uni-bremen.de/peid=ieee-9218569&Exemplar=1&LAN=DE A1 Zou, Peng A1 Lin, Zhifeng A1 Shi, Xiao A1 Wu, Yingjie A1 Chen, Jianli A1 Yu, Jun A1 Chang, Yao-Wen YR 2020 K1 Time division multiplexing K1 Routing K1 Field programmable gate arrays K1 Approximation algorithms K1 Runtime K1 Very large scale integration K1 • Hardware → Electronic design automation K1 Physical Design K1 Logic Verification K1 Multi-FPGA K1 Steiner Minimum Tree SP 1 OP 6 LK http://dx.doi.org/https://doi.org/10.1109/DAC18072.2020.9218569 DO https://doi.org/10.1109/DAC18072.2020.9218569 SF ELIB - SuUB Bremen
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