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1 Ergebnisse
1
Process Simulation of Fan-Out Wafer Level Packaging: Influe..:
, In:
2020 IEEE 8th Electronics System-Integration Technology Conference (ESTC)
,
van Dijk, Marius
;
Jaeschke, Johannes
;
Wittler, Olaf
.. - p. 1-6 , 2020
Link:
https://doi.org/10.1109/ESTC48849.2020.9229852
RT T1
2020 IEEE 8th Electronics System-Integration Technology Conference (ESTC)
: T1
Process Simulation of Fan-Out Wafer Level Packaging: Influence of Material and Geometry on Warpage
UL https://suche.suub.uni-bremen.de/peid=ieee-9229852&Exemplar=1&LAN=DE A1 van Dijk, Marius A1 Jaeschke, Johannes A1 Wittler, Olaf A1 Stegmaier, Andreas A1 Schneider-Ramelow, Martin YR 2020 K1 Numerical Simulations K1 Process Simulation K1 System in Package K1 Warpage K1 Fan-Out Packaging K1 Reliability SP 1 OP 6 LK http://dx.doi.org/https://doi.org/10.1109/ESTC48849.2020.9229852 DO https://doi.org/10.1109/ESTC48849.2020.9229852 SF ELIB - SuUB Bremen
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