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1 Ergebnisse
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Vision-Based Metal Oxide Semiconductor Transistor-Level Lay..:
, In:
2020 IEEE International Conference on Signal Processing, Communications and Computing (ICSPCC)
,
Ilagan, Lorena
;
Concepcion II, Ronnie
;
Cabatuan, Melvin
. - p. 1-6 , 2020
Link:
https://doi.org/10.1109/ICSPCC50002.2020.9259514
RT T1 <cTitle>2020 IEEE International Conference on Signal Processing, Communications and Computing (ICSPCC)</cTitle>: T1 <Title>Vision-Based Metal Oxide Semiconductor Transistor-Level Layout Error Classification Using EfficientNet Model</Title> UL https://suche.suub.uni-bremen.de/peid=ieee-9259514&Exemplar=1&LAN=DE A1 Ilagan, Lorena A1 Concepcion II, Ronnie A1 Cabatuan, Melvin A1 Roque, Christian YR 2020 K1 Layout K1 Integrated circuits K1 Feature extraction K1 Integrated circuit modeling K1 Metals K1 Semiconductor device modeling K1 Logic gates K1 computer vision K1 constraint engineering K1 deep learning K1 error classification K1 integrated circuit layout SP 1 OP 6 LK http://dx.doi.org/https://doi.org/10.1109/ICSPCC50002.2020.9259514 DO https://doi.org/10.1109/ICSPCC50002.2020.9259514 SF ELIB - SuUB Bremen
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