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1 Ergebnisse
1
Generalized Convolution Simulation Stack for RRAM Device ba..:
, In:
2020 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)
,
Prabhu, Nagaraj Lakshmana
;
Raghavan, Nagarajan
- p. 1-6 , 2020
Link:
https://doi.org/10.1109/IPFA49335.2020.9260681
RT T1
2020 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)
: T1
Generalized Convolution Simulation Stack for RRAM Device based Deep Learning Neural Network
UL https://suche.suub.uni-bremen.de/peid=ieee-9260681&Exemplar=1&LAN=DE A1 Prabhu, Nagaraj Lakshmana A1 Raghavan, Nagarajan YR 2020 SN 1946-1550 K1 Convolution K1 Logic gates K1 Hardware design languages K1 Pipelines K1 Adders K1 Image edge detection K1 Performance evaluation K1 Hardware Description Language K1 Resistive Switching Memory K1 Simulation Framework SP 1 OP 6 LK http://dx.doi.org/https://doi.org/10.1109/IPFA49335.2020.9260681 DO https://doi.org/10.1109/IPFA49335.2020.9260681 SF ELIB - SuUB Bremen
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