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1 Ergebnisse
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Design of Tunnel Junction Engineered Dopingless TFET for Lo..:
, In:
2020 International Symposium on Devices, Circuits and Systems (ISDCS)
,
Verma, Abhishek
;
Sharma, Suruchi
;
Bharti, Sneha
.. - p. 1-6 , 2020
Link:
https://doi.org/10.1109/ISDCS49393.2020.9262986
RT T1 <cTitle>2020 International Symposium on Devices, Circuits and Systems (ISDCS)</cTitle>: T1 <Title>Design of Tunnel Junction Engineered Dopingless TFET for Low power Applications</Title> UL https://suche.suub.uni-bremen.de/peid=ieee-9262986&Exemplar=1&LAN=DE A1 Verma, Abhishek A1 Sharma, Suruchi A1 Bharti, Sneha A1 Bharti, Manisha A1 Kaur, Baljit YR 2020 K1 Logic gates K1 Gallium arsenide K1 Capacitance K1 Tunneling K1 TFETs K1 Silicon K1 Junctions K1 Non-local BTBT K1 Tunneling Junction K1 charge plasma concept K1 GaAs K1 Subthreshold swing SP 1 OP 6 LK http://dx.doi.org/https://doi.org/10.1109/ISDCS49393.2020.9262986 DO https://doi.org/10.1109/ISDCS49393.2020.9262986 SF ELIB - SuUB Bremen
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