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Design and Implementation of 64-bit Parallel Prefix Adder:
, In:
2020 IEEE International Conference on Distributed Computing, VLSI, Electrical Circuits and Robotics (DISCOVER)
,
R, Akash Kumar
;
Shetty, Ashish Ashok
;
Saud, Mohammed
.. - p. 159-164 , 2020
Link:
https://doi.org/10.1109/DISCOVER50404.2020.9278102
RT T1 <cTitle>2020 IEEE International Conference on Distributed Computing, VLSI, Electrical Circuits and Robotics (DISCOVER)</cTitle>: T1 <Title>Design and Implementation of 64-bit Parallel Prefix Adder</Title> UL https://suche.suub.uni-bremen.de/peid=ieee-9278102&Exemplar=1&LAN=DE A1 R, Akash Kumar A1 Shetty, Ashish Ashok A1 Saud, Mohammed A1 Serrao, Preemal Sharanya A1 Pinto, Rohan YR 2020 K1 Adders K1 Delays K1 Logic gates K1 Propagation delay K1 Mathematical model K1 Signal processing algorithms K1 Power demand K1 parallel prefix adder K1 ling adder K1 VLSI implementation K1 fast adder SP 159 OP 164 LK http://dx.doi.org/https://doi.org/10.1109/DISCOVER50404.2020.9278102 DO https://doi.org/10.1109/DISCOVER50404.2020.9278102 SF ELIB - SuUB Bremen
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