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1 Ergebnisse
1
Impact of Process Variability on Threshold Voltage in JLAM-..:
, In:
2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)
,
Jiang, Hao-Feng
;
Li, Cong
;
Guo, Jia-Min
... - p. 1-3 , 2020
Link:
https://doi.org/10.1109/ICSICT49897.2020.9278163
RT T1
2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)
: T1
Impact of Process Variability on Threshold Voltage in JLAM-VSN-FET
UL https://suche.suub.uni-bremen.de/peid=ieee-9278163&Exemplar=1&LAN=DE A1 Jiang, Hao-Feng A1 Li, Cong A1 Guo, Jia-Min A1 Liu, Fei-Chen A1 Guo, Zeng-Guang A1 Zhuang, Yi-Qi YR 2020 K1 Resource description framework K1 Logic gates K1 Metals K1 Degradation K1 Doping K1 Semiconductor process modeling K1 Nanoscale devices SP 1 OP 3 LK http://dx.doi.org/https://doi.org/10.1109/ICSICT49897.2020.9278163 DO https://doi.org/10.1109/ICSICT49897.2020.9278163 SF ELIB - SuUB Bremen
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