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1
Development of Cascaded Multilevel Inverter Topology:
, In:
2020 IEEE First International Conference on Smart Technologies for Power, Energy and Control (STPEC)
,
Gajbhiye, Kalyani M.
;
Borghate, Vijay B.
;
Pandey, Manisha
.. - p. 1-6 , 2020
Link:
https://doi.org/10.1109/STPEC49749.2020.9297797
RT T1 <cTitle>2020 IEEE First International Conference on Smart Technologies for Power, Energy and Control (STPEC)</cTitle>: T1 <Title>Development of Cascaded Multilevel Inverter Topology</Title> UL https://suche.suub.uni-bremen.de/peid=ieee-9297797&Exemplar=1&LAN=DE A1 Gajbhiye, Kalyani M. A1 Borghate, Vijay B. A1 Pandey, Manisha A1 Sabyasachi, Sidharth A1 Gobburi, Hari babu YR 2020 K1 Topology K1 Switches K1 Gate drivers K1 Capacitors K1 Integrated circuits K1 Electrical engineering K1 Logic gates K1 multilevel inverter(MLI) K1 symmetrical and asymmetrical configuration K1 total harmonic distortion(THD) SP 1 OP 6 LK http://dx.doi.org/https://doi.org/10.1109/STPEC49749.2020.9297797 DO https://doi.org/10.1109/STPEC49749.2020.9297797 SF ELIB - SuUB Bremen
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