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1 Ergebnisse
1
A 72-nW 440-mV Time Register Using Stacked-NMOS-Switched Ga..:
, In:
2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)
,
Chen, Guowei
;
Cong Bui, Dang
;
Yu, Xinyang
... - p. 220-223 , 2020
Link:
https://doi.org/10.1109/APCCAS50809.2020.9301716
RT T1 <cTitle>2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)</cTitle>: T1 <Title>A 72-nW 440-mV Time Register Using Stacked-NMOS-Switched Gated Delay Cell in Biomedical Applications</Title> UL https://suche.suub.uni-bremen.de/peid=ieee-9301716&Exemplar=1&LAN=DE A1 Chen, Guowei A1 Cong Bui, Dang A1 Yu, Xinyang A1 Zahidul Islam, Md. A1 Kobayashi, Atsuki A1 Niitsu, Kiichi YR 2020 K1 Registers K1 Switches K1 Logic gates K1 Delays K1 Linearity K1 Computer architecture K1 Transistors K1 Biomedical applications K1 gated delay cell K1 low power K1 time information K1 time register SP 220 OP 223 LK http://dx.doi.org/https://doi.org/10.1109/APCCAS50809.2020.9301716 DO https://doi.org/10.1109/APCCAS50809.2020.9301716 SF ELIB - SuUB Bremen
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