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1 Ergebnisse
1
Built-in Stress effects of IC package substrate's layers on..:
, In:
2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC)
,
Kim, Min-Sung
;
Jung, Hyeon-Jun
;
Park, Sung-Hoon
... - p. 73-76 , 2020
Link:
https://doi.org/10.1109/EPTC50525.2020.9315057
RT T1 <cTitle>2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC)</cTitle>: T1 <Title>Built-in Stress effects of IC package substrate's layers on its warpage at room temperature</Title> UL https://suche.suub.uni-bremen.de/peid=ieee-9315057&Exemplar=1&LAN=DE A1 Kim, Min-Sung A1 Jung, Hyeon-Jun A1 Park, Sung-Hoon A1 Kim, Tae-Hyung A1 Ahn, Eun-Chul A1 Young-Hwan YR 2020 K1 Stress K1 Copper K1 Substrates K1 Temperature measurement K1 Plating K1 Stress measurement K1 Curing SP 73 OP 76 LK http://dx.doi.org/https://doi.org/10.1109/EPTC50525.2020.9315057 DO https://doi.org/10.1109/EPTC50525.2020.9315057 SF ELIB - SuUB Bremen
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