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A 32-channel FPGA-based multi-phase sampling TDC for RPC de..:
, In:
2020 IEEE 3rd International Conference on Automation, Electronics and Electrical Engineering (AUTEEE)
,
Xue, Zhengwei
;
Liang, Hao
;
Deng, Fanshui
. - p. 14-18 , 2020
Link:
https://doi.org/10.1109/AUTEEE50969.2020.9315718
RT T1 <cTitle>2020 IEEE 3rd International Conference on Automation, Electronics and Electrical Engineering (AUTEEE)</cTitle>: T1 <Title>A 32-channel FPGA-based multi-phase sampling TDC for RPC detector</Title> UL https://suche.suub.uni-bremen.de/peid=ieee-9315718&Exemplar=1&LAN=DE A1 Xue, Zhengwei A1 Liang, Hao A1 Deng, Fanshui A1 Ge, Jiajin YR 2020 K1 Clocks K1 Standards K1 Field programmable gate arrays K1 Signal resolution K1 Flip-flops K1 Detectors K1 Jitter K1 FPGA K1 multi-phase clock sampling K1 RPC K1 time resolution K1 dark count rate SP 14 OP 18 LK http://dx.doi.org/https://doi.org/10.1109/AUTEEE50969.2020.9315718 DO https://doi.org/10.1109/AUTEEE50969.2020.9315718 SF ELIB - SuUB Bremen
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