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1 Ergebnisse
1
Two-stage amplifier design based on experimental Line-Tunne..:
, In:
2019 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)
,
Filho, Walter Goncalez
;
Martino, Joao A.
;
Rangel, Roberto
... - p. 1-3 , 2019
Link:
https://doi.org/10.1109/S3S46989.2019.9320637
RT T1
2019 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)
: T1
Two-stage amplifier design based on experimental Line-Tunnel FET data
UL https://suche.suub.uni-bremen.de/peid=ieee-9320637&Exemplar=1&LAN=DE A1 Filho, Walter Goncalez A1 Martino, Joao A. A1 Rangel, Roberto A1 Agopian, Paula G. D. A1 Simoen, Eddy A1 Rooyackers, Rita A1 Claeys, Cor A1 Collaert, Nadine YR 2019 K1 TFETs K1 Logic gates K1 Tunneling K1 MOSFET K1 Bandwidth K1 Topology K1 Gain K1 Line-TFET K1 analog circuit design K1 two-stage amplifier SP 1 OP 3 LK http://dx.doi.org/https://doi.org/10.1109/S3S46989.2019.9320637 DO https://doi.org/10.1109/S3S46989.2019.9320637 SF ELIB - SuUB Bremen
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