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1 Ergebnisse
1
A ReRAM Memory Compiler with Layout-Precise Performance Eva..:
, In:
2019 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)
,
Lee, Edward
;
Kim, Daehyun
;
Chekuri, Venkata Chaitanya Krishna
.. - p. 1-3 , 2019
Link:
https://doi.org/10.1109/S3S46989.2019.9320750
RT T1
2019 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)
: T1
A ReRAM Memory Compiler with Layout-Precise Performance Evaluation
UL https://suche.suub.uni-bremen.de/peid=ieee-9320750&Exemplar=1&LAN=DE A1 Lee, Edward A1 Kim, Daehyun A1 Chekuri, Venkata Chaitanya Krishna A1 Long, Yun A1 Mukhopadhyay, Saibal YR 2019 K1 Layout K1 Random access memory K1 Tools K1 Computer architecture K1 Semiconductor device modeling K1 Microprocessors K1 Performance evaluation K1 ReRAM K1 DSE K1 Memory Compiler K1 EDA SP 1 OP 3 LK http://dx.doi.org/https://doi.org/10.1109/S3S46989.2019.9320750 DO https://doi.org/10.1109/S3S46989.2019.9320750 SF ELIB - SuUB Bremen
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