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1 Ergebnisse
1
Deep Neural Network Training Accelerator Designs in ASIC an..:
, In:
2020 International SoC Design Conference (ISOCC)
,
Venkataramanaiah, Shreyas K.
;
Yin, Shihui
;
Cao, Yu
. - p. 21-22 , 2020
Link:
https://doi.org/10.1109/ISOCC50952.2020.9333063
RT T1
2020 International SoC Design Conference (ISOCC)
: T1
Deep Neural Network Training Accelerator Designs in ASIC and FPGA
UL https://suche.suub.uni-bremen.de/peid=ieee-9333063&Exemplar=1&LAN=DE A1 Venkataramanaiah, Shreyas K. A1 Yin, Shihui A1 Cao, Yu A1 Seo, Jae-Sun YR 2020 K1 Training K1 Neural networks K1 Hardware K1 Acceleration K1 Field programmable gate arrays K1 on-device training K1 convolutional neural networks K1 hardware accelerator K1 energy efficiency SP 21 OP 22 LK http://dx.doi.org/https://doi.org/10.1109/ISOCC50952.2020.9333063 DO https://doi.org/10.1109/ISOCC50952.2020.9333063 SF ELIB - SuUB Bremen
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