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1 Ergebnisse
1
CompAcc: Efficient Hardware Realization for Processing Comp..:
, In:
2020 IEEE Asian Solid-State Circuits Conference (A-SSCC)
,
Ji, Zexi
;
Jung, Wanyeong
;
Woo, Jongchan
... - p. 1-4 , 2020
Link:
https://doi.org/10.1109/A-SSCC48613.2020.9336148
RT T1 <cTitle>2020 IEEE Asian Solid-State Circuits Conference (A-SSCC)</cTitle>: T1 <Title>CompAcc: Efficient Hardware Realization for Processing Compressed Neural Networks Using Accumulator Arrays</Title> UL https://suche.suub.uni-bremen.de/peid=ieee-9336148&Exemplar=1&LAN=DE A1 Ji, Zexi A1 Jung, Wanyeong A1 Woo, Jongchan A1 Sethi, Khushal A1 Lu, Shih-Lien A1 Chandrakasan, Anantha P. YR 2020 K1 Image coding K1 Microarchitecture K1 Conferences K1 Neural networks K1 Hardware K1 Solid state circuits K1 Computational efficiency SP 1 OP 4 LK http://dx.doi.org/https://doi.org/10.1109/A-SSCC48613.2020.9336148 DO https://doi.org/10.1109/A-SSCC48613.2020.9336148 SF ELIB - SuUB Bremen
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