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1 Ergebnisse
1
Simulation-based test algorithm generation and port schedul..:
, In:
Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232)
,
Chi-Feng Wu
;
Chih-Tsun Huang
;
Kuo-Liang Cheng
.. - p. 301,302,303,304,305,306 , 2001
Link:
https://doi.org/10.1145/378239.378491
RT T1
Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232)
: T1
Simulation-based test algorithm generation and port scheduling for multi-port memories
UL https://suche.suub.uni-bremen.de/peid=ieee-935524&Exemplar=1&LAN=DE A1 Chi-Feng Wu A1 Chih-Tsun Huang A1 Kuo-Liang Cheng A1 Chih-Wea Wang A1 Cheng-Wen Wu YR 2001 SN 0738-100X K1 Scheduling algorithm K1 Circuit faults K1 Circuit testing K1 Automatic testing K1 Built-in self-test K1 Permission K1 Circuit simulation K1 Fault diagnosis K1 Processor scheduling K1 Bandwidth SP 301,302,303,304,305,306 LK http://dx.doi.org/https://doi.org/10.1145/378239.378491 DO https://doi.org/10.1145/378239.378491 SF ELIB - SuUB Bremen
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