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1 Ergebnisse
1
Minimizing Wirelength with Bend Reduction using Gradient De..:
, In:
2021 Devices for Integrated Circuit (DevIC)
,
Nath, Subhrapratim
;
Shankar, Aditya
;
Sarkar, Ritankar
... - p. 401-405 , 2021
Link:
https://doi.org/10.1109/DevIC50843.2021.9455851
RT T1
2021 Devices for Integrated Circuit (DevIC)
: T1
Minimizing Wirelength with Bend Reduction using Gradient Descent PSO Hybrid in VLSI Global Routing
UL https://suche.suub.uni-bremen.de/peid=ieee-9455851&Exemplar=1&LAN=DE A1 Nath, Subhrapratim A1 Shankar, Aditya A1 Sarkar, Ritankar A1 Banerjee, Suharta A1 Sing, Jamuna Kanta A1 Sarkar, Subir Kumar YR 2021 K1 Wiring K1 Very large scale integration K1 Benchmark testing K1 Routing K1 Delays K1 Power dissipation K1 Transistors K1 VLSI Global Routing K1 Bend Reduction K1 RSMT K1 PSO K1 Gradient Descent SP 401 OP 405 LK http://dx.doi.org/https://doi.org/10.1109/DevIC50843.2021.9455851 DO https://doi.org/10.1109/DevIC50843.2021.9455851 SF ELIB - SuUB Bremen
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