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The Effect of Instruction Format on the CPU Performance:
, In:
2021 IEEE 1st International Maghreb Meeting of the Conference on Sciences and Techniques of Automatic Control and Computer Engineering MI-STA
,
Elahresh, Musbah Mohammed
;
Mohamed Anan, Abdrazag
- p. 327-332 , 2021
Link:
https://doi.org/10.1109/MI-STA52233.2021.9464491
RT T1 <cTitle>2021 IEEE 1st International Maghreb Meeting of the Conference on Sciences and Techniques of Automatic Control and Computer Engineering MI-STA</cTitle>: T1 <Title>The Effect of Instruction Format on the CPU Performance</Title> UL https://suche.suub.uni-bremen.de/peid=ieee-9464491&Exemplar=1&LAN=DE A1 Elahresh, Musbah Mohammed A1 Mohamed Anan, Abdrazag YR 2021 K1 Fault tolerance K1 Microprocessors K1 Conferences K1 Fault tolerant systems K1 Reliability engineering K1 Hardware K1 Safety K1 fault tolerance K1 errors K1 faults K1 failur K1 error coverage K1 error latency K1 error detection K1 fault injection SP 327 OP 332 LK http://dx.doi.org/https://doi.org/10.1109/MI-STA52233.2021.9464491 DO https://doi.org/10.1109/MI-STA52233.2021.9464491 SF ELIB - SuUB Bremen
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