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1 Ergebnisse
1
A 2 Kbit Memory Array of Mixed-VT GC-eDRAM Implemented in 1..:
, In:
2021 IEEE Regional Symposium on Micro and Nanoelectronics (RSM)
,
Abdo, Hussien
;
Alias, N. Ezaila
;
Hamzah, Afiq
... - p. 153-156 , 2021
Link:
https://doi.org/10.1109/RSM52397.2021.9511591
RT T1 <cTitle>2021 IEEE Regional Symposium on Micro and Nanoelectronics (RSM)</cTitle>: T1 <Title>A 2 Kbit Memory Array of Mixed-VT GC-eDRAM Implemented in 130nm Standard CMOS Technology</Title> UL https://suche.suub.uni-bremen.de/peid=ieee-9511591&Exemplar=1&LAN=DE A1 Abdo, Hussien A1 Alias, N. Ezaila A1 Hamzah, Afiq A1 Kamisian, Izam A1 Peng Tan, M. L. A1 Sheikh, U. Ullah YR 2021 SN 2639-4642 K1 Semiconductor device modeling K1 Power demand K1 Memory management K1 SRAM cells K1 Stability analysis K1 Software K1 Topology K1 GC-eDRAM K1 data retention time K1 performance K1 leakage power K1 two-port operation SP 153 OP 156 LK http://dx.doi.org/https://doi.org/10.1109/RSM52397.2021.9511591 DO https://doi.org/10.1109/RSM52397.2021.9511591 SF ELIB - SuUB Bremen
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