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1 Ergebnisse
1
Design of an ASIC-Based High Speed 32-bit Floating Point Ad..:
, In:
2021 International Conference on Applied Electronics (AE)
,
Deka, Debarshi
;
Kumar, Navaneeth
;
Pal, Dipankar
- p. 1-4 , 2021
Link:
https://doi.org/10.23919/AE51540.2021.9542881
RT T1
2021 International Conference on Applied Electronics (AE)
: T1
Design of an ASIC-Based High Speed 32-bit Floating Point Adder
UL https://suche.suub.uni-bremen.de/peid=ieee-9542881&Exemplar=1&LAN=DE A1 Deka, Debarshi A1 Kumar, Navaneeth A1 Pal, Dipankar YR 2021 SN 1805-9597 SN 1803-7232 K1 Computer vision K1 Computational modeling K1 Imaging K1 Machine learning K1 Prediction algorithms K1 Delays K1 Hardware design languages K1 ASIC K1 Floating Point Adder K1 Far and Close Data Path Algorithm K1 Cadence Genus and Innovus K1 Kogge-Stone Adder K1 Barrel Shifter K1 Leading One Predictor (LOP) K1 Compound Adder K1 Normalized K1 Denormalized and Mixed numbers SP 1 OP 4 LK http://dx.doi.org/https://doi.org/10.23919/AE51540.2021.9542881 DO https://doi.org/10.23919/AE51540.2021.9542881 SF ELIB - SuUB Bremen
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