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1 Ergebnisse
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A Sub-50fs-Jitter Sub-Sampling PLL with a Harmonic-Enhanced..:
, In:
ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC)
,
Zhang, Yan
;
Liang, Chia-Jen
;
Chen, Christopher
... - p. 435-438 , 2021
Link:
https://doi.org/10.1109/ESSCIRC53450.2021.9567834
RT T1 <cTitle>ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC)</cTitle>: T1 <Title>A Sub-50fs-Jitter Sub-Sampling PLL with a Harmonic-Enhanced 30-GHz-Fundemental Class-C VCO in 0.18µm SiGe BiCMOS</Title> UL https://suche.suub.uni-bremen.de/peid=ieee-9567834&Exemplar=1&LAN=DE A1 Zhang, Yan A1 Liang, Chia-Jen A1 Chen, Christopher A1 Liu, Andrew A1 Woo, Jason A1 Pamarti, Sudhakar A1 Yang, Chih-Kong Ken A1 Chang, Mau-Chung Frank YR 2021 K1 Power demand K1 Voltage-controlled oscillators K1 Resonant frequency K1 Prototypes K1 Jitter K1 BiCMOS integrated circuits K1 Transformers K1 voltage-controlled oscillators (VCO) K1 phase-locked loops (PLL) K1 millimeter-wave (mmW) K1 30GHz K1 SiGe BiCMOS SP 435 OP 438 LK http://dx.doi.org/https://doi.org/10.1109/ESSCIRC53450.2021.9567834 DO https://doi.org/10.1109/ESSCIRC53450.2021.9567834 SF ELIB - SuUB Bremen
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