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Optimization of the chip area in 3.3 kV SiC submodules for ..:
, In:
2021 23rd European Conference on Power Electronics and Applications (EPE'21 ECCE Europe)
,
Bergmann, Lukas
;
Wahle, Marcus
;
Bakran, Mark-M.
- p. 1-10 , 2021
Link:
https://doi.org/10.23919/EPE21ECCEEurope50061.2021.957..
RT T1 <cTitle>2021 23rd European Conference on Power Electronics and Applications (EPE'21 ECCE Europe)</cTitle>: T1 <Title>Optimization of the chip area in 3.3 kV SiC submodules for HVDC converters</Title> UL https://suche.suub.uni-bremen.de/peid=ieee-9570447&Exemplar=1&LAN=DE A1 Bergmann, Lukas A1 Wahle, Marcus A1 Bakran, Mark-M. YR 2021 K1 Multilevel converters K1 MOSFET K1 Silicon carbide K1 Photonic band gap K1 HVDC transmission K1 Europe K1 Silicon K1 HVDC K1 Modular Multilevel Converters (MMC) K1 Silicon Carbide (SiC) K1 Design optimization K1 Wide bandgap SP 1 OP 10 LK http://dx.doi.org/https://doi.org/10.23919/EPE21ECCEEurope50061.2021.9570447 DO https://doi.org/10.23919/EPE21ECCEEurope50061.2021.9570447 SF ELIB - SuUB Bremen
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