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1 Ergebnisse
1
Time-delay Digital Tanlock Loop based demodulators in FPGA:
, In:
2021 IEEE Mysore Sub Section International Conference (MysuruCon)
,
Pilli, Raghu
;
S, Geetha
;
Narasimhan, N. Lakshmi
... - p. 18-23 , 2021
Link:
https://doi.org/10.1109/MysuruCon52639.2021.9641619
RT T1 <cTitle>2021 IEEE Mysore Sub Section International Conference (MysuruCon)</cTitle>: T1 <Title>Time-delay Digital Tanlock Loop based demodulators in FPGA</Title> UL https://suche.suub.uni-bremen.de/peid=ieee-9641619&Exemplar=1&LAN=DE A1 Pilli, Raghu A1 S, Geetha A1 Narasimhan, N. Lakshmi A1 Soman, Jothy A1 Bhargav, Pawan Kumar A1 Sura, P. S. YR 2021 K1 Time-frequency analysis K1 VHDL K1 Satellites K1 Bit error rate K1 Frequency shift keying K1 Hardware K1 Binary phase shift keying K1 Non-uniform sampling K1 phase-locked loop K1 arc-tan phase detection K1 Demodulation K1 TDTL K1 DPLL K1 FPGA SP 18 OP 23 LK http://dx.doi.org/https://doi.org/10.1109/MysuruCon52639.2021.9641619 DO https://doi.org/10.1109/MysuruCon52639.2021.9641619 SF ELIB - SuUB Bremen
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