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Implementation and Performance Analysis of 2:1 Multiplexer ..:
, In:
2021 3rd International Conference on Advances in Computing, Communication Control and Networking (ICAC3N)
,
Siddaiah, N.
;
Bhaskar, J. S. B. B.
;
Vidya, B.
. - p. 1122-1126 , 2021
Link:
https://doi.org/10.1109/ICAC3N53548.2021.9725706
RT T1
2021 3rd International Conference on Advances in Computing, Communication Control and Networking (ICAC3N)
: T1
Implementation and Performance Analysis of 2:1 Multiplexer using Different Logic Families at 130nm Technology
UL https://suche.suub.uni-bremen.de/peid=ieee-9725706&Exemplar=1&LAN=DE A1 Siddaiah, N. A1 Bhaskar, J. S. B. B. A1 Vidya, B. A1 Reddy, V. Nagi YR 2021 K1 Multiplexing K1 Graphics K1 Optimized production technology K1 Very large scale integration K1 Logic gates K1 Inverters K1 Delays K1 Multiplexer K1 CMOS K1 Domino K1 Dual-Rail Domino K1 Pseudo NMOS K1 power delay SP 1122 OP 1126 LK http://dx.doi.org/https://doi.org/10.1109/ICAC3N53548.2021.9725706 DO https://doi.org/10.1109/ICAC3N53548.2021.9725706 SF ELIB - SuUB Bremen
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