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1 Ergebnisse
1
Design Implementation of a Low-Power 16T 1-bit Hybrid Full ..:
, In:
2021 International Conference on Control, Automation, Power and Signal Processing (CAPS)
,
Kanojia, Ayush
;
Agrawal, Sachin
;
Lorenzo, Rohit
- p. 1-5 , 2021
Link:
https://doi.org/10.1109/CAPS52117.2021.9730701
RT T1
2021 International Conference on Control, Automation, Power and Signal Processing (CAPS)
: T1
Design Implementation of a Low-Power 16T 1-bit Hybrid Full Adder
UL https://suche.suub.uni-bremen.de/peid=ieee-9730701&Exemplar=1&LAN=DE A1 Kanojia, Ayush A1 Agrawal, Sachin A1 Lorenzo, Rohit YR 2021 K1 Performance evaluation K1 Power demand K1 Simulation K1 Layout K1 Logic gates K1 Signal processing K1 Hybrid power systems K1 hybrid style adder K1 low power K1 transmission gates SP 1 OP 5 LK http://dx.doi.org/https://doi.org/10.1109/CAPS52117.2021.9730701 DO https://doi.org/10.1109/CAPS52117.2021.9730701 SF ELIB - SuUB Bremen
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