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1
Processor Extensions for Hardware Instruction Replay agains..:
, In:
2022 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)
,
Manssour, Noura Ait
;
LapOtre, Vianney
;
Gogniat, Guy
. - p. 26-31 , 2022
Link:
https://doi.org/10.1109/DDECS54261.2022.9770170
RT T1 <cTitle>2022 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)</cTitle>: T1 <Title>Processor Extensions for Hardware Instruction Replay against Fault Injection Attacks</Title> UL https://suche.suub.uni-bremen.de/peid=ieee-9770170&Exemplar=1&LAN=DE A1 Manssour, Noura Ait A1 LapOtre, Vianney A1 Gogniat, Guy A1 Tisserand, Arnaud YR 2022 SN 2473-2117 K1 Reduced instruction set computing K1 Costs K1 Software protection K1 Computer architecture K1 Hardware K1 Silicon K1 Circuit faults K1 processor architecture K1 instruction set architecture extension K1 physical attack K1 hardware countermeasure SP 26 OP 31 LK http://dx.doi.org/https://doi.org/10.1109/DDECS54261.2022.9770170 DO https://doi.org/10.1109/DDECS54261.2022.9770170 SF ELIB - SuUB Bremen
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