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1 Ergebnisse
1
Developing Formal Models for Measuring Fault Effects Using ..:
, In:
2021 IEEE International Test Conference in Asia (ITC-Asia)
,
Hu, Wei
;
Tan, Jing
;
Wu, Lingjuan
.. - p. 1-6 , 2021
Link:
https://doi.org/10.1109/ITC-Asia53059.2021.9808799
RT T1
2021 IEEE International Test Conference in Asia (ITC-Asia)
: T1
Developing Formal Models for Measuring Fault Effects Using Functional EDA Tools
UL https://suche.suub.uni-bremen.de/peid=ieee-9808799&Exemplar=1&LAN=DE A1 Hu, Wei A1 Tan, Jing A1 Wu, Lingjuan A1 Tai, Yu A1 Hong, Liang YR 2021 SN 2768-069X K1 Integrated circuit synthesis K1 Fault diagnosis K1 Fault tolerance K1 Fault tolerant systems K1 Logic gates K1 Logic functions K1 Hardware K1 Fault effect K1 fault propagation K1 formal model K1 property driven EDA SP 1 OP 6 LK http://dx.doi.org/https://doi.org/10.1109/ITC-Asia53059.2021.9808799 DO https://doi.org/10.1109/ITC-Asia53059.2021.9808799 SF ELIB - SuUB Bremen
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