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1 Ergebnisse
1
DC and Analog/RF Performance Analysis of Gate-Drain Underla..:
, In:
2022 IEEE VLSI Device Circuit and System (VLSI DCS)
,
Ghosh, Sudipta
;
Bose, Sayan
;
Anwar, Wahid
... - p. 70-74 , 2022
Link:
https://doi.org/10.1109/VLSIDCS53788.2022.9811483
RT T1
2022 IEEE VLSI Device Circuit and System (VLSI DCS)
: T1
DC and Analog/RF Performance Analysis of Gate-Drain Underlapped and Channel Engineered TFET
UL https://suche.suub.uni-bremen.de/peid=ieee-9811483&Exemplar=1&LAN=DE A1 Ghosh, Sudipta A1 Bose, Sayan A1 Anwar, Wahid A1 Banerjee, Madhusree A1 Venkateswaran, P. A1 Sarkar, Subir Kumar YR 2022 K1 Performance evaluation K1 Radio frequency K1 TFETs K1 Logic gates K1 Very large scale integration K1 Capacitance K1 Structural engineering K1 Dual material double gate TFET K1 drain underlapping K1 parasitic capacitances K1 RF analysis K1 subthreshold slope SP 70 OP 74 LK http://dx.doi.org/https://doi.org/10.1109/VLSIDCS53788.2022.9811483 DO https://doi.org/10.1109/VLSIDCS53788.2022.9811483 SF ELIB - SuUB Bremen
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