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Real Number Modeling of a SAR ADC behavior using SystemVeri..:
, In:
2022 18th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)
,
Sapsanis, Christos
;
Villemur, Martin
;
Andreou, Andreas G.
- p. 1-4 , 2022
Link:
https://doi.org/10.1109/SMACD55068.2022.9816309
RT T1
2022 18th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)
: T1
Real Number Modeling of a SAR ADC behavior using SystemVerilog
UL https://suche.suub.uni-bremen.de/peid=ieee-9816309&Exemplar=1&LAN=DE A1 Sapsanis, Christos A1 Villemur, Martin A1 Andreou, Andreas G. YR 2022 K1 Semiconductor device modeling K1 Fabrication K1 Analytical models K1 SPICE K1 Registers K1 Behavioral sciences K1 Integrated circuit modeling K1 SystemVerilog K1 behavioral model K1 real number modeling K1 model verification K1 SAR K1 ADC K1 offset cancellation SP 1 OP 4 LK http://dx.doi.org/https://doi.org/10.1109/SMACD55068.2022.9816309 DO https://doi.org/10.1109/SMACD55068.2022.9816309 SF ELIB - SuUB Bremen
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