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1 Ergebnisse
1
Fast and Accurate post-layout simulation methodology using ..:
, In:
2022 IEEE 31st Microelectronics Design & Test Symposium (MDTS)
,
Lee, Woonggyu
;
Park, Jihoon
;
Park, Jaehong
... - p. 1-5 , 2022
Link:
https://doi.org/10.1109/MDTS54894.2022.9826968
RT T1
2022 IEEE 31st Microelectronics Design & Test Symposium (MDTS)
: T1
Fast and Accurate post-layout simulation methodology using 4nm LVS rule deck
UL https://suche.suub.uni-bremen.de/peid=ieee-9826968&Exemplar=1&LAN=DE A1 Lee, Woonggyu A1 Park, Jihoon A1 Park, Jaehong A1 Park, Yongjae A1 Kim, Minkyung A1 Lee, Taehyung A1 Kim, Hyojin A1 Shin, Changyoon A1 Lee, Jiseon A1 Jung, Seungjae A1 Koo, Bonhyuck A1 Lee, Sungjae A1 Kye, Jongwook YR 2022 SN 2573-7600 K1 Runtime K1 Simulation K1 Layout K1 Electrostatic discharges K1 IP networks K1 Integrated circuit modeling K1 LVS K1 PDK K1 Post-Layout simulation SP 1 OP 5 LK http://dx.doi.org/https://doi.org/10.1109/MDTS54894.2022.9826968 DO https://doi.org/10.1109/MDTS54894.2022.9826968 SF ELIB - SuUB Bremen
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