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A 2-Layer Transistor Pixel Stacked CMOS Image Sensor with O..:

, In: 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits),

Zaitsu, K. ; Matsumoto, A. ; Nishida, M.... - p. 286-287 , 2022

Link: https://doi.org/10.1109/VLSITechnologyandCir46769.2022..

RT 
T1 <cTitle>2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)</cTitle>: T1 <Title>A 2-Layer Transistor Pixel Stacked CMOS Image Sensor with Oxide-Based Full Trench Isolation for Large Full Well Capacity and High Quantum Efficiency</Title>

UL https://suche.suub.uni-bremen.de/peid=ieee-9830372&Exemplar=1&LAN=DE
				
A1 Zaitsu, K.
A1 Matsumoto, A.
A1 Nishida, M.
A1 Tanaka, Y.
A1 Yamashita, H.
A1 Satake, Y.
A1 Watanabe, T.
A1 Araki, K.
A1 Nei, N.
A1 Nakazawa, K.
A1 Yamamoto, J.
A1 Uehara, M.
A1 Kawashima, H.
A1 Kobayashi, Y.
A1 Hirano, T.
A1 Tatani, K.
YR 2022
SN 2158-9682
K1 Resistance
K1 Three-dimensional displays
K1 Absorption
K1 Very large scale integration
K1 CMOS image sensors
K1 CMOS technology
K1 Silicon
K1 CMOS image sensor
K1 2-Layer Transistor Pixel
K1 3D sequential process
K1 full trench isolation
K1 submicron pixel
SP 286
OP 287
LK http://dx.doi.org/https://doi.org/10.1109/VLSITechnologyandCir46769.2022.9830372
DO https://doi.org/10.1109/VLSITechnologyandCir46769.2022.9830372
SF ELIB - SuUB Bremen

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