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1 Ergebnisse
1
Standard Cell Design Optimization with Advanced MOL Technol..:
, In:
2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)
,
Yang, Giyoung
;
Jung, Hakchul
;
Lim, Jinyoung
... - p. 363-364 , 2022
Link:
https://doi.org/10.1109/VLSITechnologyandCir46769.2022..
RT T1 <cTitle>2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)</cTitle>: T1 <Title>Standard Cell Design Optimization with Advanced MOL Technology in 3nm GAA Process</Title> UL https://suche.suub.uni-bremen.de/peid=ieee-9830450&Exemplar=1&LAN=DE A1 Yang, Giyoung A1 Jung, Hakchul A1 Lim, Jinyoung A1 Seo, Jaewoo A1 Kim, Ingyum A1 Yu, Jisu A1 You, Hyeoungyu A1 Kong, Jeongsoon A1 Kim, Garoom A1 Jeong, Minjae A1 Park, Chanhee A1 An, Sera A1 Rim, Woojin A1 Kim, Hayoung A1 Lee, Dalhee A1 Baek, Sanghoon A1 Jung, Jonghoon A1 Song, Taejoong A1 Kye, Jongwook YR 2022 SN 2158-9682 K1 Resistance K1 Latches K1 Gallium arsenide K1 Layout K1 Metals K1 Logic gates K1 Very large scale integration SP 363 OP 364 LK http://dx.doi.org/https://doi.org/10.1109/VLSITechnologyandCir46769.2022.9830450 DO https://doi.org/10.1109/VLSITechnologyandCir46769.2022.9830450 SF ELIB - SuUB Bremen
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