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1 Ergebnisse
1
PPAC of sheet-based CFET configurations for 4 track design ..:
, In:
2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)
,
Schuddinck, P.
;
Bufler, F. M.
;
Xiang, Y.
... - p. 365-366 , 2022
Link:
https://doi.org/10.1109/VLSITechnologyandCir46769.2022..
RT T1 <cTitle>2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)</cTitle>: T1 <Title>PPAC of sheet-based CFET configurations for 4 track design with 16nm metal pitch</Title> UL https://suche.suub.uni-bremen.de/peid=ieee-9830492&Exemplar=1&LAN=DE A1 Schuddinck, P. A1 Bufler, F. M. A1 Xiang, Y. A1 Farokhnejad, A. A1 Mirabelli, G. A1 Vandooren, A. A1 Chehab, B. A1 Gupta, A. A1 Neve, C. Roda A1 Hellings, G. A1 Ryckaert, J. YR 2022 SN 2158-9682 K1 Performance evaluation K1 Costs K1 Three-dimensional displays K1 Layout K1 Metals K1 Crystals K1 Logic gates K1 PPAC K1 CFET K1 forksheet K1 scaling K1 SAGM K1 HOT SP 365 OP 366 LK http://dx.doi.org/https://doi.org/10.1109/VLSITechnologyandCir46769.2022.9830492 DO https://doi.org/10.1109/VLSITechnologyandCir46769.2022.9830492 SF ELIB - SuUB Bremen
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