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Methodology for Active Junction Profile Extraction in thin ..:

, In: 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits),

Frutuoso, T. Mota ; Garros, X. ; Batude, P.... - p. 332-333 , 2022

Link: https://doi.org/10.1109/VLSITechnologyandCir46769.2022..

RT 
T1 <cTitle>2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)</cTitle>: T1 <Title>Methodology for Active Junction Profile Extraction in thin film FD-SOI Enabling performance driver identification in 500°C devices for 3D sequential integration</Title>

UL https://suche.suub.uni-bremen.de/peid=ieee-9830504&Exemplar=1&LAN=DE
				
A1 Frutuoso, T. Mota
A1 Garros, X.
A1 Batude, P.
A1 Brunet, L.
A1 Lacord, J.
A1 Sklenard, B.
A1 Lapras, V.
A1 Fenouillet-Beranger, C.
A1 Ribotta, M.
A1 Magalhaes-Lucas, A.
A1 Kanyandekwe, J.
A1 Kies, R.
A1 Romano, G.
A1 Catapano, E.
A1 Casse, M.
A1 Lugo-Alvarez, J.
A1 Ferrari, P.
A1 Gaillard, F.
YR 2022
SN 2158-9682
K1 Performance evaluation
K1 Resistance
K1 Three-dimensional displays
K1 Silicon-on-insulator
K1 Very large scale integration
K1 Predictive models
K1 Capacitance
SP 332
OP 333
LK http://dx.doi.org/https://doi.org/10.1109/VLSITechnologyandCir46769.2022.9830504
DO https://doi.org/10.1109/VLSITechnologyandCir46769.2022.9830504
SF ELIB - SuUB Bremen

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