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1 Ergebnisse
1
Hardware Design of Combinational 128-bit Camellia Symmetric..:
, In:
2022 IEEE International Conference on Semiconductor Electronics (ICSE)
,
Sak, Chawalit Udom
;
Naziri, Siti Zarina Md
;
Ismail, Rizalafande Che
.. - p. 101-104 , 2022
Link:
https://doi.org/10.1109/ICSE56004.2022.9863201
RT T1
2022 IEEE International Conference on Semiconductor Electronics (ICSE)
: T1
Hardware Design of Combinational 128-bit Camellia Symmetric Cipher using 0.18µm Technology
UL https://suche.suub.uni-bremen.de/peid=ieee-9863201&Exemplar=1&LAN=DE A1 Sak, Chawalit Udom A1 Naziri, Siti Zarina Md A1 Ismail, Rizalafande Che A1 Isa, Mohd Nazrin Md A1 Hussin, Razaidi YR 2022 K1 Ciphers K1 Schedules K1 Power demand K1 Microprocessors K1 Computer architecture K1 Hardware K1 Timing K1 Camellia cipher K1 128-bit K1 Symmetric cipher K1 ASIC K1 O.18Jlm K1 Cryptography K1 Verilog SP 101 OP 104 LK http://dx.doi.org/https://doi.org/10.1109/ICSE56004.2022.9863201 DO https://doi.org/10.1109/ICSE56004.2022.9863201 SF ELIB - SuUB Bremen
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