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1 Ergebnisse
1
A Method to Reduce Jitter Due to Power Noise by Optimizing ..:
, In:
2022 Asia-Pacific International Symposium on Electromagnetic Compatibility (APEMC)
,
Wu, Haojie
;
Wang, Wenrui
;
Ye, Lingyun
.. - p. 616-619 , 2022
Link:
https://doi.org/10.1109/APEMC53576.2022.9888438
RT T1 <cTitle>2022 Asia-Pacific International Symposium on Electromagnetic Compatibility (APEMC)</cTitle>: T1 <Title>A Method to Reduce Jitter Due to Power Noise by Optimizing Loop Filter in PLL Based Clock Source</Title> UL https://suche.suub.uni-bremen.de/peid=ieee-9888438&Exemplar=1&LAN=DE A1 Wu, Haojie A1 Wang, Wenrui A1 Ye, Lingyun A1 Song, Kaichen A1 Sun, Xinglin YR 2022 SN 2640-7469 K1 Phase noise K1 Power supplies K1 Simulation K1 Printed circuits K1 Jitter K1 Sensors K1 Phase locked loops K1 power supply noise K1 clock jitter K1 phase-locked loop K1 loop bandwidth SP 616 OP 619 LK http://dx.doi.org/https://doi.org/10.1109/APEMC53576.2022.9888438 DO https://doi.org/10.1109/APEMC53576.2022.9888438 SF ELIB - SuUB Bremen
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