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On the benefits of Collaborative Thread Throttling and HLS-..:
, In:
2022 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI)
,
Knorst, Tiago
;
Korol, Guilherme
;
Jordan, Michael Guilherme
... - p. 1-6 , 2022
Link:
https://doi.org/10.1109/SBCCI55532.2022.9893223
RT T1 <cTitle>2022 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI)</cTitle>: T1 <Title>On the benefits of Collaborative Thread Throttling and HLS-Versioning in CPU-FPGA Environments</Title> UL https://suche.suub.uni-bremen.de/peid=ieee-9893223&Exemplar=1&LAN=DE A1 Knorst, Tiago A1 Korol, Guilherme A1 Jordan, Michael Guilherme A1 Vicenzi, Julio Costella A1 Lorenzon, Arthur A1 Rutzig, Mateus Beck A1 Beck, Antonio Carlos Schneider YR 2022 K1 Performance evaluation K1 Collaboration K1 Central Processing Unit K1 Kernel K1 Optimization K1 System analysis and design K1 Field programmable gate arrays K1 CPU-FPGA K1 throttling K1 Collaborative K1 TLP SP 1 OP 6 LK http://dx.doi.org/https://doi.org/10.1109/SBCCI55532.2022.9893223 DO https://doi.org/10.1109/SBCCI55532.2022.9893223 SF ELIB - SuUB Bremen
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