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1 Ergebnisse
1
A 56-Gb/s PAM4 Transceiver with False-Lock-Aware Locking Sc..:
, In:
ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC)
,
Tachibana, Fumihiko
;
Ngo, Huy Cu
;
Urakawa, Go
... - p. 505-508 , 2022
Link:
https://doi.org/10.1109/ESSCIRC55480.2022.9911409
RT T1 <cTitle>ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC)</cTitle>: T1 <Title>A 56-Gb/s PAM4 Transceiver with False-Lock-Aware Locking Scheme for Mueller-Müller CDR</Title> UL https://suche.suub.uni-bremen.de/peid=ieee-9911409&Exemplar=1&LAN=DE A1 Tachibana, Fumihiko A1 Ngo, Huy Cu A1 Urakawa, Go A1 Toi, Takashi A1 Ashida, Mitsuyuki A1 Tsubouchi, Yuta A1 Nozawa, Mai A1 Wadatsumi, Junji A1 Kobayashi, Hiroyuki A1 Deguchi, Jun YR 2022 K1 Europe K1 FinFETs K1 CMOS technology K1 Transceivers K1 Solid state circuits K1 Registers K1 Phase locked loops K1 baud-rate CDR K1 PAM4 K1 false-lock-aware K1 phase adjustment SP 505 OP 508 LK http://dx.doi.org/https://doi.org/10.1109/ESSCIRC55480.2022.9911409 DO https://doi.org/10.1109/ESSCIRC55480.2022.9911409 SF ELIB - SuUB Bremen
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