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Deriving FSM-based tests using $a,b-\text{faults}$ for Logi..:
, In:
2022 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
,
Laputenko, Andrey
;
Yevtushenko, Nina
;
Andreeva, Valentina
. - p. 80-85 , 2022
Link:
https://doi.org/10.1109/ISVLSI54635.2022.00027
RT T1
2022 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
: T1
Deriving FSM-based tests using $a,b-\text{faults}$ for Logic Circuits
UL https://suche.suub.uni-bremen.de/peid=ieee-9912030&Exemplar=1&LAN=DE A1 Laputenko, Andrey A1 Yevtushenko, Nina A1 Andreeva, Valentina A1 Matrosova, Anzhela YR 2022 SN 2159-3477 K1 Boolean functions K1 Latches K1 Automata K1 Very large scale integration K1 Libraries K1 Sequential circuits K1 Behavioral sciences K1 finite state machine K1 logic circuit K1 testing SP 80 OP 85 LK http://dx.doi.org/https://doi.org/10.1109/ISVLSI54635.2022.00027 DO https://doi.org/10.1109/ISVLSI54635.2022.00027 SF ELIB - SuUB Bremen
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