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1
Possible Reductions to Generate circuits from BDDs:
, In:
2022 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
,
Brandao, Eduarde D.
;
Nespolo, Joao P.
;
Peralta, Renato D.
.. - p. 406-409 , 2022
Link:
https://doi.org/10.1109/ISVLSI54635.2022.00091
RT T1
2022 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
: T1
Possible Reductions to Generate circuits from BDDs
UL https://suche.suub.uni-bremen.de/peid=ieee-9912075&Exemplar=1&LAN=DE A1 Brandao, Eduarde D. A1 Nespolo, Joao P. A1 Peralta, Renato D. A1 Butzen, Paulo F. A1 Reis, Andre I. YR 2022 SN 2159-3477 K1 Multiplexing K1 Systematics K1 Boolean functions K1 Binary decision diagrams K1 Very large scale integration K1 Inverters K1 Decision trees K1 Digital circuits K1 BDDs - Binary Decision Dia-grams K1 multiplexer circuits K1 AIGs - And Inverter Graphs SP 406 OP 409 LK http://dx.doi.org/https://doi.org/10.1109/ISVLSI54635.2022.00091 DO https://doi.org/10.1109/ISVLSI54635.2022.00091 SF ELIB - SuUB Bremen
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