I agree that this site is using cookies. You can find further informations
here
.
X
Login
Merkliste (
0
)
Home
About us
Home About us
Our history
Profile
Press & public relations
Friends
The library in figures
Exhibitions
Projects
Training, internships, careers
Films
Services & Information
Home Services & Information
Lending and interlibrary loans
Returns and renewals
Training and library tours
My Account
Library cards
New to the library?
Download Information
Opening hours
Learning spaces
PC, WLAN, copy, scan and print
Catalogs and collections
Home Catalogs and Collections
Rare books and manuscripts
Digital collections
Subject Areas
Our sites
Home Our sites
Central Library
Law Library (Juridicum)
BB Business and Economics (BB11)
BB Physics and Electrical Engineering
TB Engineering and Social Sciences
TB Economics and Nautical Sciences
TB Music
TB Art & Design
TB Bremerhaven
Contact the library
Home Contact the library
Staff Directory
Open access & publishing
Home Open access & publishing
Reference management: Citavi & RefWorks
Publishing documents
Open Access in Bremen
zur Desktop-Version
Toggle navigation
Merkliste
1 Ergebnisse
1
Fairness in Multiprocessor Hardware Access to System-on-Chi:
, In:
2022 IEEE 5th International Symposium in Robotics and Manufacturing Automation (ROMA)
,
Rokon, M. I. R.
;
Motakabber, S. M. A.
;
Zahirul Alam, A. H. M.
.. - p. 1-6 , 2022
Link:
https://doi.org/10.1109/ROMA55875.2022.9915675
RT T1 <cTitle>2022 IEEE 5th International Symposium in Robotics and Manufacturing Automation (ROMA)</cTitle>: T1 <Title>Fairness in Multiprocessor Hardware Access to System-on-Chip</Title> UL https://suche.suub.uni-bremen.de/peid=ieee-9915675&Exemplar=1&LAN=DE A1 Rokon, M. I. R. A1 Motakabber, S. M. A. A1 Zahirul Alam, A. H. M. A1 Habaebi, M. Hadi A1 Matin, M. A. YR 2022 K1 Adaptation models K1 Hardware K1 Foundries K1 System-on-chip K1 Hardware design languages K1 Round robin K1 Field programmable gate arrays K1 AMBA Bus Protocol K1 Processor Inteface K1 Multiprocessor Round Robin Arbitration K1 HDL Methodology K1 Verilog K1 Simulation K1 Synthesis K1 FPGA SP 1 OP 6 LK http://dx.doi.org/https://doi.org/10.1109/ROMA55875.2022.9915675 DO https://doi.org/10.1109/ROMA55875.2022.9915675 SF ELIB - SuUB Bremen
Export
RefWorks (nur Desktop-Version!)
Flow
(Zuerst in
Flow
einloggen, dann importieren)
