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HiRA: Hidden Row Activation for Reducing Refresh Latency of..:
, In:
2022 55th IEEE/ACM International Symposium on Microarchitecture (MICRO)
,
Yaglikci, A. Giray
;
Olgun, Ataberk
;
Patel, Minesh
... - p. 815-834 , 2022
Link:
https://doi.org/10.1109/MICRO56248.2022.00062
RT T1 <cTitle>2022 55th IEEE/ACM International Symposium on Microarchitecture (MICRO)</cTitle>: T1 <Title>HiRA: Hidden Row Activation for Reducing Refresh Latency of Off-the-Shelf DRAM Chips</Title> UL https://suche.suub.uni-bremen.de/peid=ieee-9923850&Exemplar=1&LAN=DE A1 Yaglikci, A. Giray A1 Olgun, Ataberk A1 Patel, Minesh A1 Luo, Haocong A1 Hassan, Hasan A1 Orosa, Lois A1 Ergin, Oguz A1 Mutlu, Onur YR 2022 K1 Degradation K1 Microarchitecture K1 System performance K1 Standards organizations K1 Failure analysis K1 Parallel processing K1 DRAM chips K1 DRAM K1 memory controller K1 refresh K1 rowhammer K1 memory access latency SP 815 OP 834 LK http://dx.doi.org/https://doi.org/10.1109/MICRO56248.2022.00062 DO https://doi.org/10.1109/MICRO56248.2022.00062 SF ELIB - SuUB Bremen
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