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Influence of the SiC JFET Gate Impedance on the Off-State V..:
, In:
2022 IEEE Workshop on Wide Bandgap Power Devices and Applications in Europe (WiPDA Europe)
,
Mendy, Simon
;
Agbo, Nereus Sunday
;
Gonzalez, Jose Ortiz
. - p. 1-6 , 2022
Link:
https://doi.org/10.1109/WiPDAEurope55971.2022.9936268
RT T1
2022 IEEE Workshop on Wide Bandgap Power Devices and Applications in Europe (WiPDA Europe)
: T1
Influence of the SiC JFET Gate Impedance on the Off-State Voltage Balance in Cascode Configuration
UL https://suche.suub.uni-bremen.de/peid=ieee-9936268&Exemplar=1&LAN=DE A1 Mendy, Simon A1 Agbo, Nereus Sunday A1 Gonzalez, Jose Ortiz A1 Alatise, Olayiwola YR 2022 K1 Resistance K1 Semiconductor device modeling K1 MOSFET K1 Silicon carbide K1 Europe K1 Switches K1 Logic gates K1 SiC JFET K1 silicon MOSFET K1 SiC Cascode K1 Compact Modelling K1 State-space modelling K1 Parasitics K1 Gate Impedance SP 1 OP 6 LK http://dx.doi.org/https://doi.org/10.1109/WiPDAEurope55971.2022.9936268 DO https://doi.org/10.1109/WiPDAEurope55971.2022.9936268 SF ELIB - SuUB Bremen
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