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1 Ergebnisse
1
Cache-Major: A Hardware Architecture and Scheduling Policy ..:
, In:
2022 IEEE 16th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)
,
Cheng, Jinhui
;
Liu, Xuanzhi
;
Cao, Yue
... - p. 1-3 , 2022
Link:
https://doi.org/10.1109/ICSICT55466.2022.9963310
RT T1 <cTitle>2022 IEEE 16th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)</cTitle>: T1 <Title>Cache-Major: A Hardware Architecture and Scheduling Policy for Improving DRAM Access Efficiency in GEMV</Title> UL https://suche.suub.uni-bremen.de/peid=ieee-9963310&Exemplar=1&LAN=DE A1 Cheng, Jinhui A1 Liu, Xuanzhi A1 Cao, Yue A1 Zhang, Wenjun A1 Han, Zhongze A1 Peng, Bo A1 Liu, Yixuan A1 Zhang, Donglin A1 Han, Yongkang A1 Xu, Xiaoxin A1 Yang, Jianguo YR 2022 K1 Out of order K1 Integrated circuit technology K1 Processor scheduling K1 High performance computing K1 Memory management K1 Random access memory K1 Bandwidth SP 1 OP 3 LK http://dx.doi.org/https://doi.org/10.1109/ICSICT55466.2022.9963310 DO https://doi.org/10.1109/ICSICT55466.2022.9963310 SF ELIB - SuUB Bremen
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