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1 Ergebnisse
1
Congestion estimation with buffer planning in floorplan des..:
, In:
Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition
,
Chiu-Wing Sham
;
Wai-Chiu Wong
;
Young, E.R.Y.
- p. 696,697,698,699,700,701 , 2002
Link:
https://doi.org/10.1109/DATE.2002.998375
RT T1
Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition
: T1
Congestion estimation with buffer planning in floorplan design
UL https://suche.suub.uni-bremen.de/peid=ieee-998375&Exemplar=1&LAN=DE A1 Chiu-Wing Sham A1 Wai-Chiu Wong A1 Young, E.R.Y. YR 2002 SN 1530-1591 K1 Delay K1 Routing K1 Integrated circuit interconnections K1 Timing K1 Dynamic programming K1 Very large scale integration K1 Shape K1 Transistors K1 Clocks K1 Minimization SP 696,697,698,699,700,701 LK http://dx.doi.org/https://doi.org/10.1109/DATE.2002.998375 DO https://doi.org/10.1109/DATE.2002.998375 SF ELIB - SuUB Bremen
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