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Order-lot pegging for minimizing total tardiness in semicon..:
Kim, J-G
;
Lim, S-K
The Journal of the Operational Research Society. 63 (2012) 9 - p. 1258-1270 , 2012
Link:
https://www.jstor.org/stable/23251200
RT Journal T1
Order-lot pegging for minimizing total tardiness in semiconductor wafer fabrication process
UL https://suche.suub.uni-bremen.de/peid=jstor-23251200&Exemplar=1&LAN=DE A1 Kim, J-G A1 Lim, S-K PB Palgrave Macmillan YR 2012 SN 0160-5682 SN 1476-9360 K1 Applied sciences K1 Engineering K1 Electrical engineering K1 Electronic components K1 Active components K1 Semiconductors K1 Semiconductor wafers K1 Business K1 Business economics K1 Commercial production K1 Production resources K1 Resource management K1 Time management K1 Lateness K1 Industrial engineering K1 Manufacturing engineering K1 Manufacturing K1 Mathematics K1 Mathematical objects K1 Mathematical sequences K1 Computer science K1 Algorithms K1 Scheduling K1 Mathematical procedures K1 Mathematical optimization K1 Optimal solutions K1 Behavioral sciences K1 Psychology K1 Cognitive psychology K1 Decision theory K1 Operations research K1 Cognitive processes K1 Problem solving K1 Heuristics JF The Journal of the Operational Research Society VO 63 IS 9 SP 1258 OP 1270 LK http://dx.doi.org/https://www.jstor.org/stable/23251200 DO https://www.jstor.org/stable/23251200 SF ELIB - SuUB Bremen
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